An EPROM has several structures which allow it to hold a charge without refresh for extended periods of time (see FIG. 1). The charge itself is stored on a "floating gate" 10 also referred to as Poly 1 or P1, which is a structure of polycrystalline silicon surrounded on all sides by a layer of oxide 12. Located superjacent and parallel to this P1 structure is another poly structure, the "control gate" 14 or P2. P1 10 and P2 14 act as the two plates of a capacitor. Below the P1 layer are two N+ junctions, one which acts as the transistor source 16 and the other as the drain 18, which are doped into a p-type substrate 20. The portion of the substrate 20 between the source 16 and the drain 18 is the channel 22. The cell of FIG. 1 functions like an enhancement-type n-channel metal oxide semiconductor field effect transistor (MOSFET) with two gates of polysilicon.
To program an E.sup.2 PROM, a ground voltage is applied either on the drain or the source. Simultaneously, a large voltage, for example 25 V, is applied to the control gate. An n-type inversion layer (channel) is created at the substrate surface below the floating gate as a result of the large voltage applied to the control gate. The large positive voltage on the control gate (greater than the drain voltage) establishes an electric field in the insulating oxide. This electric field attracts the electrons and accelerates them toward the floating gate, which they enter through a "tunneling window" in the oxide. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped.
To return the floating gate from a charged state to a state with no charge, the charge is returned to the substrate. In an EPROM, this is accomplished with ultraviolet light which excites the electrons past a certain energy state, thereby allowing them to pass through the oxide and return to the substrate. In an E.sup.2 PROM, this excitation is accomplished with an electrical field.
The voltage which must be applied on the control gate to turn on the transistor (i.e. the threshold voltage V.sub.t) is much higher in a device storing a charge than in a device which does not have a voltage potential stored on P1. To read the content of the floating gate, a voltage somewhere between the low and high threshold values is applied to the control gate. A cell that trips at this intermediate voltage has no charge stored on P1, while a cell which does not trip is determined to be storing a charge.
As with most electronic devices, design engineers attempt to devise PROMs which use as little power as possible in order to increase integration density of the PROM. This includes power used to program the PROMS as well as operating power. One way to decrease power consumption is to decrease the cell size, which also serves to decrease the time it takes to access the information on the floating gate. Decreasing the size of an EPROM includes decreasing the width of P1 and P2, with a similar reduction in the width of the channel. Decreasing the P1 and P2 widths, however, decreases the coupling capacitance between P1 and P2, which increases the likelihood of errors while reading the cell charge.
The floating gate of an EPROM forms a capacitor with the control gate, as described above, and also with the source, the drain, and the channel. This arrangement is described in FIG. 2. If the surface areas of P1 and/or P2 are increased, P1 and P2 can be reduced in width while maintaining the same coupling capacitance between P1 and P2. The coupling capacitances associated with P1 are described by the coupling coefficient, which is depicted by the equation (referring to FIG. 2) EQU CC=C1/(C1+C2+C3+C4)
where CC is the coupling coefficient, C1 represents the coupling between P1 and P2, C2 represents the coupling between P1 and the source, C3 represents the coupling between P1 and the drain, and C4 represents the coupling between P1 and the channel. As an example, if C1=0.5, C2=0.1, C3=0.1, and C4=0.3, the coupling coefficient would equal 0.5 (50%). If the area of the surface of P1 proximal to P2 is increased by 100%, C1 would increase to 1.0, and CC would increase to 0.67 (67%). With this increase, the size of P1 and P2 could be decreased by 50%, which would reduce CC by 17% back to the original 50%. As can be determined from the equation, the coupling coefficient can never reach the ideal state (1.00) since the capacitance between the floating gate and the control gate is always divided by itself plus some additional capacitance. Still, the goal of designers is to bring the coupling coefficient as close to unity as possible.
Texturized (rough or rugged) polysilicon has been used with varying success in the manufacture of certain types of semiconductor devices. It has been used with dynamic random access memories (DRAMs), for example, to increase the surface area of the storage node cell plate. This increases the charge that can be stored on the node, and allows a decrease in the size of the DRAM, and therefore an increase in the density of the DRAM, while maintaining an equal charge on each storage node.
Rugged poly on semiconductor devices has been accomplished in mainly two ways. The first way is to control the temperature at which the poly is deposited. If the poly is deposited at a narrow temperature band around 570.degree. C. (.+-.3.degree. C.) a rough texture is imparted to the poly, thereby increasing the surface area of the poly. A second way the poly surface is ruggedized is to oxidize the poly and etch it with hydrofluoric acid. Regardless of the method, any material such as oxide, which is then deposited on top of the rough poly, will itself be texturized. If the layer of material deposited on the texturized poly is thin, both its lower and upper surface will be texturized. A thick layer of material will be texturized on its lower surface, but untexturized on its upper surface.
Rugged poly has been used in the manufacture of some E.sup.2 PROMs to increase the electrical field intensity through the tunneling window in the substrate to make it easier to transfer electrons to the floating gate, thereby increasing program efficiency. For example, U.S. Pat. No. 4,947,221 describes the use of rugged poly on the upper surface of a floating gate on an EPROM. The use of rugged poly decreases the distance between the floating gate and the control gate, and therefore increases leakage between the two gates, thereby requiring less power to program the device. With this device, the tunneling window is between the control gate and the floating gate. The reduced distance of the two gates through the oxide layer between them makes it easier for the electrons to tunnel through the oxide layer.